Priority is claimed to Japanese Patent Application Number JP2005-098967 filed on Mar. 30, 2005, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device which reduces an ON resistance value and realizes a large current by use of a structure of a drain region.
2. Description of the Related Art
As a conventional semiconductor device, the following technology has been known. For example, in a CMOS transistor, a P-type well region and an N-type well region are formed on a silicon substrate. In the P-type well region, an N-channel MOS transistor is formed. In the N-type well region, a P-channel MOS transistor is formed. For example, in the N-channel MOS transistor, source and drain regions having an LDD structure are formed in the P-type well region. In this event, the source and drain regions are formed by ion-implanting N-type impurities into the P-type well region formed on the silicon substrate. This technology is described for instance in Japanese Patent Application Publication No. 2004-140404.
Moreover, as a conventional semiconductor device, the following technology has been known. For example, in an N-channel MOS semiconductor device, an N-type epitaxial layer is deposited on a P-type single crystal silicon substrate. In the N-type epitaxial layer, a P-type well region is formed. In the P-type well region, an N-type source region is formed. The P-type well region is formed so as to extend to a part below a gate electrode on the N-type epitaxial layer. In the N-type epitaxial layer, an N-type drain region is formed in the vicinity of the P-type well region. Moreover, a gate oxide film is formed to be thick on the drain region side and to be thin on the source region side. This structure of the gate oxide film prevents a variation in characteristics of a silicon oxide film due to a high electric field on the drain region side. This technology is described for instance in Japanese Patent Application Publication No. 2002-314065.
As described above, in the conventional semiconductor device, the N-type source and drain regions are formed in the P-type well region in the N-channel MOS transistor of the CMOS transistor. Accordingly, an impurity concentration of the P-type well region and an impurity concentration of the N-type source and drain regions offset each other. Thus, it is difficult to obtain desired impurity concentrations. In the case where the N-type source and drain regions are set to be high-concentration impurity regions, a formation region of a depletion layer is reduced. Thus, there arises a problem that a withstand pressure of the MOS transistor is deteriorated. Moreover, in the case where the impurity concentration of the P-type well region is set low, the formation region of the depletion layer on a channel side is increased. Thus, there arises a problem that a formation region of the MOS transistor is increased.
Moreover, in the conventional semiconductor device, the gate oxide film may be formed to be thick on the drain region side and to be thin on the source region side in the N-channel MOS transistor. In this case, the drain region is formed so as to extend to a part below a gate electrode the thick gate oxide film. Moreover, in the P-type well region, a channel region is formed so as to be distant from the drain region. By adopting the structure described above, the P-type well region and the drain region are formed to be distant from each other, and a current path is increased in length. Thus, there arises a problem that an ON resistance value is increased. Furthermore, by forming the gate oxide film so as to vary in thickness, a manufacturing process is complicated. Thus, there arises a problem that the manufacturing costs.